The present invention relates to a semiconductor device that has MISFETs, each having a gate electrode and an insulating film called xe2x80x9cside wallxe2x80x9d on the sides of the gate electrode. More particularly, the invention relates to an integrated circuit that operates with at least two operating voltages, such as a flash EEPROM which operates with an input voltage generated outside the chip externally applied and a high voltage generated inside the chip.
FIG. 1 shows a conventional MISFET.
A gate insulating film 12 is formed on the semiconductor substrate 11. A gate insulating film 13 is formed on the gate insulating film 12. An insulating film 14 called xe2x80x9cside wallxe2x80x9d is provided on the sides of the gate insulating film 12. Diffusion layers 15a, which have a low impurity concentration and known as xe2x80x9cLDDs (Lightly Doped Drains),xe2x80x9d are formed in those parts of the substrate 11 which lie beneath the side wall 14.
Beside the diffusion layers 15a, diffusion layers 15b are formed which have a higher impurity concentration than the diffusion layers 15a. A pre-metal dielectric 16 is formed on the substrate 11, covering all other parts of the MISFET. The pre-metal dielectric 16 has a contact hole 17, which reaches one of the diffusion layers 15b. The contact hole 17 is filled with a contact plug 18 made of, for example, tungsten (W). A metal wire 19 is provided on the contact plug 18.
For any LSI having MISFETs described above, the margin between the gate electrode 13 and contact hole 17 of each MISFET is one of the obstacles to the desired increase of integration density. Self-alignment contact (SAC) technique has been proposed as means for reducing the margin between the gate electrode 13 and the contact hole 17, thereby to enhance the integration density of the LSI.
FIG. 2 illustrates a conventional MISFET to which the self-alignment contact technique has been applied.
As shown in FIG. 2, a gate insulating film 12 is provided on the semiconductor substrate 11. A gate electrode 13 is formed on the gate insulating film 12. On the gate electrode 13, a cap insulating film 20 is provided which works as a mask in the process (etching) of making a contact hole 17. An insulating film 14 called xe2x80x9cside wallxe2x80x9d is provided on the sides of the cap insulating film 20. The side wall 14 also functions as a mask in the process (etching) of making the contact hole 17.
Diffusion layers 15a, which have a low impurity concentration and known as xe2x80x9cLDDs,xe2x80x9d are formed in those parts of the substrate 11 which lie beneath the side wall 14. Beside the diffusion layers 15a, diffusion layers 15b are formed which have a higher impurity concentration than the diffusion layers 15a. A premetal dielectric 16 is formed on the substrate 11, covering all other parts of the MISFET. The pre-metal dielectric 16 has the contact hole 17, which reaches one of the diffusion layers 15b. The contact hole 17 is filled with a contact plug 18 made of, for example, tungsten (W). A metal wire 19 is provided on the contact plug 18.
The MISFET shown in FIG. 2 is characterized in the following respects.
First, the side wall 14 and the cap insulating film 20 function as a mask in the process of making the contact hole 17. That is, the side wall 14, pre-metal dielectric 16 and cap insulating film 20 are made of such materials that the selectivity R2/R1, or the ratio of the etching rate R2 of the pre-metal dielectric 16 to the etching rate R1 of the side wall 14 and cap insulating film 20, is as high as possible. If the pre-metal dielectric 16 is made of, for example, silicon oxide film (e.g., BPSG film or the like), the side wall 14 and cap insulating film 20 will be made of silicon nitride film.
Second, the gate electrode 13 is always insulated from the contact plug 18 made in the contact hole 17. This is because the side wall 14 and cap insulating film 20 function as an etching mask even if the gate electrode 13 happens to overlap the contact hole 17. Thus, the margin between the gate electrode 13 and the contact hole 17 much decreases, serving to enhance the integration density of the LSI.
To enhance the integration density of an LSI having MISFETs to which the self-alignment contact technique (FIG. 2) has been applied, it is required that the side wall 14 have a minimum thickness necessary to maintain the gate electrode 13 and the contact plug 18 insulated from each other. If the side wall 14 has such a minimum thickness, the contact plug 18 can be located sufficiently close to the gate electrode 13 (or can overlap the gate electrode 13) as shown in FIG. 3. Further, contact plug 18 can have an adequate contact area (proportional to distance Sa) with one of the diffusion layers 15b as depicted in FIG. 3.
As shown in FIG. 4, however, the MISFETs may differ in the thickness of the side wall 14 in the course of processing the wafer. The side walls 14 of some MISFETs may be thicker than is desired. If the contact plug 18 is located sufficiently close to the gate electrode 13, the contact area (proportional to distance Sa) at which the contact plug 18 contacts the diffusion layers 15b will become too small. This would increase the contact resistance at the interface between the contact plug 18 and one of the diffusion layers 15b. 
FIG. 5 shows a semiconductor device that has two MISFETs sharing a diffusion layer 15bb. The shorter the distance between the gate electrodes 13 of the MISFETS, the smaller the contact area (proportional to distance Sc) between the diffusion layer 15bb and the contact plug 18. The side walls 14 of the two MISFETS, which cover the gate electrodes 13 thereof, may therefore contact each other as shown in FIG. 6. If this occurs, the contact hole 17 cannot reach the surface of the semiconductor substrate 11.
The side wall formed on the side of the gate electrode 13 of each MISFET serves not only to achieve a self-alignment contact, but also to form diffusion layers 15a and 15b of LD structure. The diffusion layers 15a and 15b of LDD structure perform various functions, such as increasing of the breakdown voltage of the p-n junction of the MISFET, mitigating of the generation of hot carriers, and inhibiting of short-channel effect.
Integrated circuits that operate with two or more operating voltages have MISFETs operating at a low voltage and MISFETs operating at a high voltage. In each MISFET operating at the low voltage, the side wall provided on the sides of the gate electrode is made as thin as possible, thereby forming short LDDS. Further, the contact hole reaching the source/drain diffusion layer is located as close as possible to the gate electrode, thereby to enhance the integration density of the LSI.
In each MISFET operating at the high voltage, the side wall provided on the sides of the gate electrode is made as thick as possible, thereby forming long LDDS. Having long LDDS, the MISFET can operate normally even if a high voltage is applied to it.
In order to enhance the integration density of the LSI and also to make the MISFETs operate normally, it is necessary to form MISFETs of at least two types, different in terms of the LDD length, in a single chip. To this end, however, it has hitherto been necessary to form two or more types of side walls, each type for the MISFETs having one LDD length. As a consequence, photo engraving process (PEP) must be repeated as many times as the types of MISFETs required, in the course of processing the wafer.
In other words, an increased number of steps must be carried out to process the wafer, inevitably increasing the cost of manufacturing the LSI. In view of this, it has been impossible, in practice, to form MISFETs of two types, different in terms of LDD length, in a single chip.
FIG. 7 shows a NOR-type flash EEPROM comprising MISFETS. The memory cells arranged in the memory cell area will be described first.
Each memory cells has a stacked gate structure. A gate insulating film 12mf is provided on the semiconductor substrate 11. A floating gate electrode 13mf is provided on the gate insulating film 12mf. An insulating film 12mc is formed on the floating gate electrode 13mf. A control gate 13mc is provided on the insulating film 12mc. An insulating film 14 called xe2x80x9cside wallxe2x80x9d is provided on the sides of the floating gate electrode 13mf and control gate 13mc. Diffusion layers 15b, which are a source and a drain, are formed in the surface of the semiconductor substrate 11.
A pre-metal dielectric 16 is formed on the semiconductor substrate 11, completely covering the memory cells of the stacked gate structure. The pre-metal dielectric 16 has contact holes 17, each reaching one of the diffusion layers (drain) 15b of each memory cell. Contact plugs 18 made of, for example, tungsten (W), are formed in the contact holes 17. Metal wires 19 are provided on the contact plugs 18.
The NOR-type flash EEPROM has a peripheral circuit area. In the peripheral circuit area, high-voltage transistors are provided. The high-voltage transistors operate at a voltage higher than the power-supply voltage VCC (3.3V, 5V or the like), which ranges, for example, from 6V to 20V.
Gate insulating films 12h are provided on the semiconductor substrate 11. Gate electrodes 13h are provided on the gate insulating films 12h. Each gate insulating film 12h is, for example, about 10 nm thick, or thick enough not to undergo dielectric breakdown when applied with the high voltage. An insulating film 14 called xe2x80x9cside wallxe2x80x9d is provided on the sides of each gate electrode 13h. 
Diffusion layers 15aa having low impurity concentration, called xe2x80x9cLDDs (Lightly Doped Drains),xe2x80x9d are formed in the surface of the semiconductor substrate 11. Further, diffusion layers 15b (sources and drains) are formed in the diffusion layers 15aa, respectively. The diffusion layers 15b have a higher impurity concentration than the diffusion layers 15aa. 
The diffusion layers 15aa are deep so that the breakdown voltage at the p-n junction of each high-voltage transistor may be higher than the operating voltage of the high-voltage transistor. Only diffusion layers 15aa are formed in those parts of the substrate 11, which lie right below each side wall 14. The diffusion layers 15aa have a length H1 that is proportional to the thickness of the side wall 14. The side wall 14 is relatively thick (e.g., about 0.2 xcexcm), so that the breakdown voltage at the p-n junction of each high-voltage transistor may be higher than the operating voltage of the high-voltage transistor.
The thickness of the diffusion layers 15aa and the thickness of the side walls 14 influences the width of the depletion layer that develops in the p-n junction area of each high-voltage transistor. The thicker the diffusion layers 15aa and side walls 14, the broader the depletion layer and, hence, the higher the breakdown voltage of the high-voltage transistor.
A pre-metal dielectric 16 is formed on the semiconductor substrate 11. The insulator 16 completely covers the MISFETs. The pre-metal dielectric 16 has contact holes 17, each reaching one diffusion layer 15b. Contact plugs 18 made of, for example, tungsten (W), are formed in the contact holes 17. Metal wires 19 are provided on the contact plugs 18.
Low voltage transistors are provided in the peripheral circuit area, too. The low voltage transistors operate at the power-supply voltage VCC (3.3V, 5V or the like), or at a voltage lower than the power-supply voltage VC.
In the peripheral circuit area, gate insulating films 12n are provided on the semiconductor substrate 11. Gate electrodes 13n are provided on the gate insulating films 12h. An insulating film 14 called xe2x80x9cside wallxe2x80x9d is provided on the sides of each gate electrode 13n. Diffusion layers 15a having low impurity concentration, called xe2x80x9cLDDs (Lightly Doped Drains),xe2x80x9d are formed in the surface of the semiconductor substrate 11, two located right below one side wall 14.
Adjacent to the respective diffusion layers 15a, diffusion layers 15b (sources and drains) are provided. The diffusion layers 15b have an impurity concentration higher than the diffusion layers 15a. A pre-metal dielectric 16 is formed on the semiconductor substrate 11, also in the peripheral circuit area. The insulator 16 completely covers the MISFETS. The pre-metal dielectric 16 has contact holes 17, each reaching one of the diffusion layers 15b of each low voltage transistor.
In the manufacture of the NOR-type flash EEPROM shown in FIG. 7, the side walls 14 provided in the MISFETs are formed at the same time in the memory cell area and the peripheral circuit area. Hence, the side walls 14 of the memory cells, those of the high-voltage transistors and those of the low voltage transistors have the same thickness.
The side walls 14 are made of silicon oxide film, silicon nitride film or the like, whereas the pre-metal dielectric 16 is made of silicon oxide film. In the case where the side walls 14 are made of silicon oxide film, there may occur errors in the alignment of the gate electrodes with respect to the contact holes.
If alignment errors occur, there will arise the risk that gate electrodes are short-circuited with the contact plugs made in the contact holes.
The side walls 14 may be made of silicon nitride film. In this case, the area (contact area) at which one diffusion layer is exposed at the bottom of one contact hole 17 will decrease if the contact hole 17 overlaps the side wall 14. This increases the contact resistance at the interface between the contact plug 18 and one of the diffusion layers 15b. To prevent the contact holes 17 from overlapping the side walls 14, respectively, the margin (width) H2 between each gate electrode and the adjacent contact hole is set at a sufficient value. More specifically, the margin H2 is the sum of the thickness L1 of the side walls 14 and the margin L2 between the side wall 14 and the contact hole. The margin L2 is determined from the accuracy of aligning a mask in the photo engraving process (PEP) and the dimensional precision of the contact hole 17.
For example, the margin (width) H2 between the gate electrode and the adjacent contact hole will be 0.4 xcexcm if the side wall 14 has a thickness L1 of 0.2 xcexcm and the margin L2 between the gate electrode and the contact hole 17 is 0.2 xcexcm.
Thus, if the side walls 14 are made of material that is more hardly etched than the pre-metal dielectric 16 (e.g., silicon nitride film), the margin H2 between each side wall 14 and the adjacent contact hole 17 must be sufficiently large. Otherwise, the contact hole 17 would overlap the side wall 14. If the margin H2 is increased, however, the MISFETs (including the memory cells) will become large, which is undesirable in view of the enhancement of the integration density of the LSI and the desired reduction of the chip area.
In the NOR-type flash EEPROM, the memory cells have no LDDs. As far as the memory cells are concerned, the side walls 14 are not necessary. Nonetheless, each memory cell has a side wall to facilitate or simplify the processing of the wafer. As a consequence, every memory cell of the NOR-type flash EEPROM is larger by the thickness L1 of the side wall 14 than those, which have no side walls.
The thickness L1 of each side wall 14 is determined so as to impart sufficiently high breakdown voltage to the p-n junction of each high-voltage transistor. Hence, the side wall 14 of each low voltage transistor is excessively thick, and the diffusion layers 15a (LDDS) of each low voltage transistor have an excessive length L3. The low voltage transistor is inevitably large, having an on-resistance. The low voltage transistors will have but inadequate driving capacity.
The object of the present invention is to provide a semiconductor device, in which MISFETS (normal transistor or low voltage transistor) operating at a low voltage have short LDDs and self-alignment structure, thus serving to increase the integration density of an LSI without causing an increase in the contact resistance, and MISFETs (high-voltage transistors) operating at a high voltage have LDDs and a sufficient margin between the gate electrode and the contact hole and a p-n junction with a sufficiently high breakdown voltage.
A semiconductor device according to the present invention comprises: a source/drain diffusion layer provided in a semiconductor substrate; an LDD diffusion layer provided in the semiconductor substrate and located adjacent to the source/drain diffusion layer; a gate electrode arranged above the semiconductor substrate; a pre-metal dielectric covering the gate electrode; a first side-wall film provided on sides of the gate electrode; and a second side-wall film provided on sides of the first side-wall film and different in material from the first side-wall film.
Another semiconductor device according to the invention comprises: a source/drain diffusion layer provided in a semiconductor substrate; a floating gate electrode arranged above the semiconductor substrate; a control gate electrode arranged above the floating gate electrode; a pre-metal dielectric covering the floating gate electrode and control gate electrode; a first side-wall film provided on sides of the floating gate electrode and control gate electrodes; and a second side-wall film provided on sides of the first side-wall film and different in material from the first side-wall film.
Still another semiconductor device according to the invention comprises: a first MISFET operating at a first operating voltage; a second MISFET operating at a second operating voltage higher than the first operating voltage; and a pre-metal dielectric covering the first and second MISFETS. The first MISFET comprises a first source/drain diffusion layer provided in a semiconductor substrate; a first LDD diffusion layer provided in the semiconductor substrate and located adjacent to the first source/drain diffusion layer; a first gate electrode arranged above the semiconductor substrate; a first side-wall film provided on sides of the first gate electrode; and a second side-wall film provided on sides of the first side-wall film and different in material from the first side-wall film. The second MISFET comprises a second source/drain diffusion layer provided in the semiconductor substrate; a second LDD diffusion layer provided in the semiconductor substrate and located adjacent to the second source/drain diffusion layer; a second gate electrode arranged above the semiconductor substrate; a third side-wall film provided on sides of the second gate electrode; and a fourth side-wall film provided on sides of the third side-wall film and different in material from the third side-wall film.
A semiconductor device according to the present invention comprises: a first MISFET operating at a first operating voltage; a second MISFET operating at a second operating voltage higher than the first operating voltage; and a pre-metal dielectric covering the first and second MISFETS. The first MISFET comprises a first source/drain diffusion layer provided in a semiconductor substrate; a first LDD diffusion layer provided in the semiconductor substrate and located adjacent to the first source/drain diffusion layer; a first gate electrode arranged above the semiconductor substrate; and a first side-wall film provided on sides of the first gate electrode. The second MISFET comprises a second source/drain diffusion layer provided in the semiconductor substrate; a second LDD diffusion layer provided in the semiconductor substrate and located adjacent to the second source/drain diffusion layer; a second gate electrode arranged above the semiconductor substrate; a second side-wall film provided adjacent to the second gate electrode; and a third side-wall film provided adjacent to the second side-wall film and different in material from the second side-wall film.
Another semiconductor device according to this invention comprises: a plurality of memory cells connected in series; and a pre-metal dielectric covering the plurality of memory cells, each comprising a source diffusion layer provided in a semiconductor substrate, a drain diffusion layer provided in the semiconductor substrate, a floating gate electrode provided above a channel area between the source and drain diffusion layers, and a control gate electrode provided above the floating gate electrode. The first of a plurality of spaces among the plurality of memory cells is broader than the second space provided above the source diffusion layer, and the second of the spaces is filled with a first side-wall film contacting sides of the floating gate electrode and control gate electrode.
A still another semiconductor device according to the invention comprises: a cell unit comprising a plurality of memory cells connected in series; a first select transistor connected to one end of the cell unit and having a source diffusion layer; a second select transistor connected to another end of the cell unit and having a drain diffusion layer; and a pre-metal dielectric covering the memory cells and the first and second select transistors. Each of the plurality of memory cells comprises diffusion layers provided in a semiconductor substrate, a floating gate electrode provided above a channel area between the diffusion layers, and a control gate electrode provided above the floating gate electrode. Each of spaces among the plurality of memory cells is filled with a first side-wall film contacting sides of the floating gate electrode and control gate electrode.
A method of manufacturing a semiconductor device, according to the present invention, comprises the steps of: forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; performing anisotropic etching on the first film, thereby forming a first side-all film on sides of the first and second gate electrodes; performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET in the semiconductor substrate; forming a second film covering the first and second gate electrode, above the semiconductor substrate; performing anisotropic etching on the second film, thereby forming a second side-all film on sides of the first and second gate electrodes; and performing ion implantation, thereby forming a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.
Another method of manufacturing a semiconductor device, according to the invention, comprises the steps of: forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; forming a second film on the first film, the second film being different in material from the first film; performing anisotropic etching on the second film, thereby forming a first side-all film at a stepped part near the first gate electrode and a stepped part near the second gate electrode; and performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET, in the semiconductor substrate.
Still another method of manufacturing a semiconductor device, according to the invention, comprises the steps of: forming, above a semiconductor substrate, a first gate electrode of a first MISFET operating at a first operating voltage and a second gate electrode of a second MISFET operating at a second operating voltage higher than the first operating voltage; performing ion implantation, thereby forming a first LDD of the first MISFET and a second LDD of the second MISFET in the semiconductor substrate; forming a first film covering the first and second gate electrodes, above the semiconductor substrate; forming a second film on the first film, the second film being different in material from the first film; performing partial etching on the second film, thereby removing a part of the second film which lies above the first MISFET and leaving the second film above the second MISFET; performing anisotropic etching on the second film, thereby forming a first side-wall film at a stepped part near the second gate electrode; performing anisotropic etching on the first film, thereby forming a second side-all film on sides of the first and second gate electrodes; and performing ion implantation, thereby forming a first source/drain diffusion layer of the first MISFET and a second source/drain diffusion layer of the second MISFET in the semiconductor substrate.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.